1. Field
Embodiments of the present invention relate to the electronics manufacturing industry and more particularly to a patterning process enabling a reduced half pitch.
2. Discussion of Related Art
Lithography is used in the manufacture of integrated circuits (ICs). FIGS. 1A-1C illustrate cross-sectional views of a conventional semiconductor lithographic process. Referring to FIG. 1A, a photoresist layer 104 is provided above a semiconductor stack 102. A mask or reticle 106 is positioned above photoresist layer 104. A lithographic process includes exposure of photoresist layer 104 to radiation (hν) having a particular wavelength (λ), as indicated by the arrows in FIG. 1A. Referring to FIG. 1B, photoresist layer 104 is subsequently developed to remove the portions photoresist layer 104 that were exposed to light and thereby provide patterned photoresist layer 108 above semiconductor stack 102. The width of each feature of patterned photoresist layer 108 is depicted by the width ‘x’ of a feature and the space ‘y’ between each feature. The width ‘x’ added to space ‘y’ is referred to as the pitch, p.
Referring to FIG. 1C, the CD, or width ‘x,’ of a feature may be reduced to form patterned photoresist layer 110 above semiconductor stack 102. The CD may be shrunk, or “biased” by over-exposing photoresist layer 104 during the lithographic step depicted in FIG. 1A or by trimming patterned photoresist layer 108 provided in FIG. 1B with an isotropic etch process prior to etching semiconductor stack 102. However, such a reduction in feature CD comes at the expense of an increased spacing between features, as depicted by spacing ‘y’ in FIG. 1C. That is, there is a trade-off between the smallest dimension of the features in patterned photoresist layer 110 and the spacing between these features, thereby making pitch a constant when feature biasing is employed.
Since biasing a pattern to reduce feature dimensions does not reduce pitch, the critical path for further IC scaling lies with the resolution of the lithographic process. The resolution limit for a particular lithographic process is characterized with features having a critical dimension (CD) equal to the space between the features, i.e. x=y, as depicted in FIG. 1B, with both x and y being equal to the “half pitch.” For example, a particular conventional 193 nm lithography system provides a minimum pitch, p, of 130 nm and a 65 nm half pitch.
Generally, the minimum half pitch may be derived from the Rayleigh resolution equation and is a function of the numerical aperture (NA) of the imaging system, the wavelength (λ) of the imaging light. Thus, some strategies to advance lithography are based on high NA lithography, such as “hyper-NA” immersion lithography wherein an NA of about 1.3 can be achieved by immersing the imaging optics in water. Still other strategies to advance lithography employ shorter wavelengths, such as extreme ultra-violet (EUV). Progress on these fronts, however, has been slow, hindered by the substantial development and re-tooling required.
As a result, the need to reach the 45 nm half pitch node and even 32 nm half pitch node in state of the art IC fabrication has arrived before availability of production-worthy lithography systems employing either high refractive index or EUV technology. Density-sensitive product lines, such as flash memory and dynamic random access memory (DRAM) are therefore pursuing double patterning lithography (DPL) as a third strategy to reduce the effective half pitch of patterns formed in a substrate. Generally, the DPL technique successively patterns a substrate twice, each patterning operation performed with a different mask and a relaxed half pitch. The two resulting patterns interlace to compose features on the substrate having a half pitch smaller than that of either individual pattern. The composition of the two patterns is then transferred into the substrate to define a pattern in the substrate having a half pitch below that lithographically achievable with the particular lithography employed, i.e. “sub-minimum half pitch.”
Because the DPL method is relatively independent of the lithographic technology employed, it can be practiced with existing 193 nm lithography as well as next generation high NA or EUV lithography to provide a sub-minimum half pitch. Thus, DPL will, sooner or later, likely become a fixture in the industry as a means to extend the capabilities of each lithography generation. DPL however is potentially cost prohibitive, particularly as a result of production cycle time, which increases because multiple photomasks, multiple resist coats and multiple etches are required to form pattern in a single layer. DPL also incurs an overlay penalty because of the plurality of masking operations. Thus, methods to reduce feature pitch without incurring such a large overhead are advantageous.